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Verification Technical Leader  - in Misgav area


For a major defense company in the area of Misgav. 

This position includes hands-on verification of FPGA modules.

Planning and implementation of verification environments using System Verilog UVM methodology.

Technical guidance of a team of 2-3 junior engineers with potential to grow



B.Sc. in Electrical Engineering (from a known university).

Minimum 2 years of experience in System Verilog UVM/OVM Verification methodology.

Clear understanding of constrained random verification process, functional coverage, code coverage and assertion methodology

Experienced with architecture, specs, documentation and debugging.

Responsibility and dedication is a must

Familiarity with verification environments/languages: VMM, Specman, System C - advantage. 



Apply now



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