Senior Backend Engineer
Backend Engineer with a vast background in chip design from RTL to GDS.
BSEE is required, MSEE is preferred.
At least 5 years experience in backend flow.
Experience with backend design for advanced CMOS processes (28nm and below).
Experienced in RTL to GDS full flow, including Synthesis, DFT, Timing, constraints, multi-clock domains, low power design and high-frequency design methodologies, P&R, physical verification, etc.