Inomize is a professional Research & Development firm specializing in designing and delivering hardware solutions. We offer a broad range of services tailored to meet your project needs.
Inomize successfully delivers ambitious projects on schedule and within budget.
We take full advantage of innovative technology, and when necessary, push it to the limits. Years of experience and proactive project management approach, allow Inomize to reduce development time and minimize the risks involved in designing complex hardware projects.
Established in 2007, Inomize is a fast-growing company and the largest Israeli ASIC design firm in Israel. Our customers include leading international corporations and start-up companies from Israel, Europe, and North America.
Inomize is a professional Research & Development firm specializing in designing and delivering hardware solutions. We offer a broad range of services tailored to meet your project needs.
Inomize successfully delivers ambitious projects on schedule and within budget.
We take full advantage of innovative technology, and when necessary, push it to the limits. Years of experience and proactive project management approach, allow Inomize to reduce development time and minimize the risks involved in designing complex hardware projects.
Established in 2007, Inomize is a fast-growing company and the largest Israeli ASIC design firm in Israel. Our customers include leading international corporations and start-up companies from Israel, Europe, and North America.
SINCE 2007
Senior ASIC Backend Designer Engineer
Job summary:
Our emerging UK branch is looking for excellent backend engineers with a vast experience in chip design from RTL to GDSII full flow.
Description:
-
The role includes responsibility for floor planning, physical synthesis and physical verification of large complex designs Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.
-
As a leading member of physical/implementation design team, drive physical design and sub-micron methodologies and “best-known methods” to streamline physical design work, come up with guidelines and checklists and drive execution.
-
Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.
-
Resolve design and flow issues related to physical design, identify potential solutions
Requirements:
Key qualification:
-
Minimum 5 years hands-on experience in backend flow.
-
Experience with large SoC designs with frequencies more than 1GHz utilizing state of the art 28nm and below technologies.
-
Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.
-
Hands on experience in block level implementation including physical synthesis, P&R, CTS and optimization
-
Well versed with timing constraints, STA and timing closure and AC timing
-
Hands on experience with Physical Design Verification Flows - LVS/DRC/Antenna
-
Experience in EM/IR-Drop/Xtalk analysis
-
Experience with low power design features and flows.
The candidate must have hands-on experience with the following Tools:
-
Floor planning and P&R tools: Cadence Innovus and/or Synopsys ICC2
-
Synthesis Tools: Synopsys DC/DCG; Cadence Genus
-
Formal Verification: Synopsys Formality and Cadence LEC
-
Static Timing verification – Primetime
-
Physical Design Verification tools
Other locations:
Netanya, Israel, 1-2 travels per year may be required
Education:
BSEE is mandatory, MSEE - an advantage.