Analog designer with block/circuit level know-how and experience.
BSEE is mandatory, MSEE/Ph.D. – an advantage.
At least 3-5 years hands-on experience in analog design.
Experience with advanced CMOS processes (45nm and below).
Experience with design modeling tools (Matlab, Verilog A) and analog simulation tools (Hspice, Spectre).
Experience with definition, design, simulation and layout review at block level for SOC,
Design experience with Analog Front End, op-amp, switch-cap filter, continuous time filter, reference or bias generation, LDO, Data conversion ADC and DAC subsystem, High speed I/O design, etc.
Solid understanding of transistor device characteristics and manufacturing process impacts.
Solid understanding of power, area and performance trade-off in mixed-signal designs.