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Backend Group Director


We are looking for a talented Director to oversee our Backend Group. This candidate will be responsible for the full ASIC backend flow from RTL to GDS for highly complex SoCs designs. The position entails 

heading up all design flow cycles including synthesis, STA, Formal, block level PnR, floor-planning, clock and power distribution, power and noise analysis (EM / IR-Drop / Xtalk), layout verification (DRC / LVS). The candidate will interface with remote sites, contractors and conduct F2F discussion with customers



  • B.Sc. in Electrical Engineering (Electronics) / Computer Engineering

  • 10+ years’ experience in Backend design of large scale SoC.

  • At least 3 years’ experience as a back-end team leader

  • Extensive experience with one of today`s available place & route tools (Synopsys / Cadence)

  • Experience with the hierarchical design approach, top-down design, timing and physical convergence

  • In-depth understanding of static-timing analysis

  • Extensive know-how in clock/power distribution and analysis, RC extraction

  • Experience with advanced CMOS process nodes (16nm/7nm)

  • Experience in integration of soft and hard IPs

  • Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration

  • Experience in scripting and programming using one or more of the following: Perl / TCL / Make;

  • Experience working in Unix environments with version control

  • Experience with Lynx flow - advantage

  • Knowledge in Verilog, DFT design – advantage

Apply now


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